In-phase and quadrature-phase signal amplitude and phase calibration

ABSTRACT

In-phase (I) and quadrature-phase (Q) signals are corrected for both amplitude and phase imbalances by passing the I and Q signals successively through a first amplitude correction stage, a sum-difference stage, and a second amplitude correction stage. The first amplitude correction stage balances the signal levels of the I and Q signals. The sum-difference stage produce a sum of the input I and Q signals, and a difference of the input I and Q signals, resulting in ideal quadrature in the outputs produced. The second amplitude correction stage corrects the amplitude differences from the sum-difference stage. Circuit configurations are used that minimize errors produced by the signal processing stages.

RELATED APPLICATIONS

This application is a continuation of U.S. Non-Provisional applicationSer. No. 11/300,046 filed Dec. 14, 2005, U.S. Pat. No. 7,570,710 issuedAug. 4, 2009 entitled “In-phase and Quadrature-phase Signal Amplitudeand Phase Calibration”; which claims priority from U.S. provisionalapplication No. 60/636,383 filed Dec. 15, 2004 entitled “In-phase andQuadrature-phase Signal Amplitude and Phase Calibration”, incorporatedherein by reference.

BACKGROUND

In receivers and transmitters, complex signals are often represented astwo real signals denoted in-phase (I) and quadrature-phase (Q). Thecomplex signal is then given as S=I+jQ where j=i√−1. Referring to FIG.1, the typical well-known quadrature receiver architecture is shownwherein RF signal 100 is down converted to I/Q signals 101, which can abaseband frequency or an IF frequency (such as in so-called “low-IF”receivers).

In FIG. 1, down conversion is illustrated for the case where the downconversion is to baseband. Spectrum of RF signal 102, the spectrum oflocal oscillator (LO) tone 103, and the resulting down convertedspectrum 104 of S=I+jQ is shown. The desired result is a frequencytranslation of the signal spectrum but as spectrum 104 shows, there willalso be an undesired image signal 105, shown hatched. This is amirror-imaged (spectrally inverted) and attenuated version of thedesired signal. The image is cause by amplitude and phase imbalancesbetween the I and Q mixing paths. Usually the phase difference is causedby imperfections in the 90-degree phase split for the I and Q LOsignals.

Up conversion from baseband I and Q signals to an IF or RF signal canalso create an undesired image even when the LO signals driving themixers are in perfect quadrature and amplitude balance. If the I and Qsignals are not amplitude and phase balanced, a spectrally invertedimage is present in the IF/RF and overlays the desired IF/RF signal.

It is desirable to reduce the image as much as possible and to this endit may be necessary calibrate the I and Q signals so as to suppressamplitude and phase errors. The calibration mechanism should preferablybe continuous so that it can track changing amplitude and phase errorsduring without interrupting reception. The errors tend to drift duringreception due to factors such as temperature, receive signal level, etc.

The conceptually most obvious way of adjusting the amplitude error issimply to insert a variable gain amplifier in either the I or Q path orboth. Similarly, the phase error can be corrected by introducing avariable phase adjustment in series with the 90 degree LO splitter. Thisleaves the challenge of devising a method for measuring amplitude andphase differences between I and Q accurately and using that informationto drive the correction circuitry. The implementation of phasecorrection and, in particular, accurate phase measurement is verychallenging, especially under the constraint of continuous calibrationbecause the properties of the received signal are in most cases unknownand therefore many well-known techniques such as zero-crossing detectionare not applicable.

Lui, U.S. Pat. No. 6,560,449, entitled “Image rejection I/Qdemodulators”, issued May 6, 2003 discloses a feedback technique forreducing the image response of a receiver. The image/signal ratio ismeasured on the demodulator I/Q mixer outputs by detecting the phase andamplitude differences of the I and Q demodulated signals, then amplitudeand phase control is applied to the quadrature LO generator driving theI and Q mixers to reduce the image response. The image/signal detectoris calibrated during interstitial intervals between data packets. Thisapproach requires interruption of the primary signal demodulation forcalibration of the detector and a phase and amplitude adjustable LOgenerator.

For these reasons, it would be desirable if the I/Q phase and amplitudebalance could be corrected without needing phase measurement orcorrection. Furthermore, it would be advantageous if this techniquecould be implemented entirely at the I/Q signals without requiring anyintervention into the sensitive RF circuits.

SUMMARY OF THE INVENTION

This invention allows for I and Q phase and amplitude balance withoutusing challenging phase measurements or corrections. The technique ofthe invention can be performed at the intermediate frequency (IF) I/Q orbaseband I/Q signals without altering the RF circuitry and withoutprocessing at RF frequencies. The I and Q signals are initially passedthrough an amplitude equalization block that balances the signal levelsbetween I and Q. The phase error is then corrected by a sum-differencecircuit, where new vectors are created from the sum and difference ofthe I and Q signals. The resulting signals are in quadrature phaserelationship, with a new amplitude imbalanced introduced. Amplitudebalancing is again performed by passing the phase corrected I and Qsignals through a second amplitude equalization block. The final resultsare I and Q signals that have quadrature-phase relationship and areequal in amplitude. By having the I and Q signals balanced, theundesired spectral image in the signal is reduced. The phase andamplitude balance can be applied to I and Q signals after downconversion from RF in a receiver or prior to up conversion to RF in atransmitter.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows prior art quadrature receiver architecture, quadrature upconversion, and illustration of the creation of an image signal duringdown conversion or up conversion.

FIG. 2 shows a block diagram of the calibration method of the presentinvention.

FIG. 3 shows the geometric manipulation of I and Q vectors to restorequadrature and balance amplitude.

FIG. 4 shows a block diagram of an amplitude equalization block for usewith the present invention.

FIG. 5 shows a block diagram of the amplitude difference detector.

FIG. 6 shows an example implementation of a summation circuit.

FIG. 7 shows prior art model of summation or difference circuit withmismatches.

FIG. 8 shows the present invention configuration for highly accuratesummation and difference circuits.

FIG. 9 shows an example timing diagram of the amplitude differencedetector.

FIG. 10 shows a quadrature up converter with I and Q calibration forimage rejection.

DETAILED DESCRIPTION OF INVENTION

FIG. 2 shows the principle of operation of the present invention.Amplitude-equalizing stage 200 is cascaded with a sum-difference circuit201 and a second amplitude-equalizing stage 202. The result is I/Qcalibration to null both the phase and amplitude imbalances.

As illustrated in FIG. 3 a, incoming I and Q signals 300 have phase andamplitude errors and are not in perfect quadrature, i.e. whenrepresented as vectors in the complex plane they are not of equal lengthand are not perpendicular.

In FIG. 3 b vector I₁ 302 and vector Q₁ 301 are the amplitude balancedvectors of the original incoming I and Q signals. Vector Q₂ 303 is thedifference of Q₁ and I₁ and vector I₂ 304 is the sum of Q₁ and I₁.Vectors Q₂ and I₂ are quadrature-phase but of unequal amplitude. Asecond amplitude equalization block corrects vectors Q₂ and I₂ to resultin Q_(out) and I_(out) signals, which are balanced in amplitude and arequadrature-phased, as illustrated in FIG. 3 c.

FIG. 4 shows an example of an amplitude equalization block, which can beimplemented as a loop that measures the amplitude difference between Iand Q using amplitude difference detector 401 and controls via controlblock 400 either one or two variable gain amplifiers 402. Alternativelyvariable attenuators may be used or a combination of gain andattenuation. The amplitude balancing requires variability in either theI or the Q path but for symmetry reasons it may be desirable to use thesame variable block in both paths, controlled in opposite directions.

This amplitude balancing and signal sum-differencing for I/Q calibrationmay be carried out in the analog domain, in the digital domain, or in acombination thereof. In an analog-focused implementation the I and Qsignals would be analog as well as the variable gain or attenuatorblocks and the amplitude difference detectors.

In a digital-focused implementation the I and Q, signals would bedigital signals, for example, a digitized version of analog signals, andthe aforementioned blocks would be digital circuits. The digital-focusedimplementation has the benefit of high precision and accuracy in thesignal processing circuit blocks. Thus, the amplitude difference caneasily be detected without measurement error. This can, for example, bedone by digital peak detection of I and Q followed by subtraction.Similarly, in a digital implementation the sum-difference block can beimplemented with no mismatch in gain between the summation paths.

FIG. 5 shows a block diagram of an exemplary embodiment of amplitudedifference detector 401 of FIG. 4.

The accuracy of the sum-difference circuit is crucial. In a digitalimplementation, this is not an issue and the sum-difference block caneasily be implemented using well-known methods. In an analogimplementation, the accuracy is more challenging. The path mismatch inthe sum-difference block is a potential issue in an analogimplementation and can cause degradation of quadrature. Using atechnique forming part of the present invention, it is possible toobtain high precision with very low sensitivity to mismatch.

FIG. 6 shows one possible implementation of a summation circuit. Thiscircuit also functions as a difference circuit by simply swapping oneset of input terminals.

The circuit uses differential signals, which is standard in basebandanalog circuits. It converts the I and Q signals to currents, which thenare summed and converted into a voltage again at the output. Matching ofthe resistors attached to the transistor collectors and emitters iscritical for the accuracy and it can require very large silicon area toachieve sufficient matching. The matching of the emitter resistors isthe most important. The resistor matching sets the α and β factors,described below.

In general the sum (or difference) function can be illustrated as shownin FIG. 7 where α, β, and γ represent gain errors due to mismatches inthe I input circuitry, Q input circuitry, and I₂ output circuitry,respectively. This model is valid for any type of implementation whetherusing the approach of FIG. 6, or using operational amplifiers, or otherimplementation.

Using the well-known concept of common-mode and differential signals, wecan write:

I ₁₊ =I _(CM1) +i ₁/2 I ¹⁻ =I _(CM1) −i ₁/2

Q ₁₊ =Q _(CM1) +q ₁/2 Q ¹⁻ =Q _(CM1) −q ₁/2

Where I₁₊ and I¹⁻ are the I₁ differential-mode signals; Q₁₊ and Q¹⁻ arethe Q₁ differential signals; I_(CM1) and Q_(CM1) represent thecommon-mode voltages for I₁ and Q₁; i₁ and q₁ represents the desireddifferential-mode components of the I and Q signals.

The effect of the mismatches is thus:

i ₂=(1+γ)((1+α)i ₁+(1+β)q ₁)

Where i₂ is the desired summed signal; α is the mismatched gain error ofthe I pair; β is the mismatched gain error of the Q pair; γ is themismatched gain error of the output I₂ pair.

The effect of γ is insignificant because it is compensated by thefollowing amplitude equalization block. However, minimizing the α and βfactors is crucial and it can require very large silicon area to achievesufficient matching for this purpose.

It is clearly desirable to devise a method in which the α and β factorshave greatly reduced influence on the summation accuracy. The methodused in the present invention is to swap input signals in an appropriatemanner.

FIG. 8 illustrates the new method, where the negative signal of eachinput pair is crossed between summer inputs, thus it is routed to theother summer input. This results in cancellation of some errorsintroduced by the circuitry of the summer.

Using the configuration of FIG. 8, we obtain:

${I_{2 +} - I_{2 -}} = {{\left( {1 + \gamma} \right)\begin{pmatrix}{{\left( {1 + \alpha} \right)\left( {I_{1 +} - Q_{1 -}} \right)} +} \\{\left( {1 + \beta} \right)\left( {Q_{1 +} - I_{1 -}} \right)}\end{pmatrix}}\mspace{95mu} = {{\left( {1 + \gamma} \right)\begin{pmatrix}{{\left( {1 + \alpha} \right)\begin{pmatrix}{I_{{CM}\; 1} + {i_{1}/2} -} \\{Q_{{CM}\; 1} + {q_{1}/2}}\end{pmatrix}} +} \\{\left( {1 + \beta} \right)\begin{pmatrix}{Q_{{CM}\; 1} + {q_{1}/2} -} \\{I_{{CM}\; 1} + {i_{1}/2}}\end{pmatrix}}\end{pmatrix}}\mspace{95mu} = {{\left( {1 + \gamma} \right)\left( {1 + \frac{\alpha + \beta}{2}} \right)\left( {i_{1} + q_{1}} \right)} + {\left( {1 + \gamma} \right)\left( {\alpha - \beta} \right)\left( {I_{{CM}\; 1} - Q_{{CM}\; 1}} \right)}}}}$

The I and Q signals are summed together with minimal error except forthe small effect of common-mode signals as explained below. The sum of Iand Q sees a slight gain error of

${\left( {1 + \gamma} \right)\left( {1 + \frac{\alpha + \beta}{2}} \right)},$

which is easily corrected by the subsequent gain equalization block.

As the equation shows, we also generate a residual common-mode todifferential-mode conversion. If I_(CM1)=Q_(CM1) this product is null.However in practical circuits there will be a small unavoidabledifferential imbalance, which manifests itself as a signal component onI_(CM1) and Q_(CM1). However, its effect of the I₂ signal accuracy isnegligible because the common-mode signal is normally very small and itis multiplied by a factor of (α−β), which is also very small.

The same method can be used for the difference block generating theQ₂₊−Q²⁻ signal, with I₁₊ and I¹⁻ swapped in order to generate asubtraction as opposed to a summation.

This circuit configuration to achieve minimization of errors isindependent of the underlying circuit implementation on the summation ordifference blocks. It only relies on a suitable reconfiguration ofdifferential input signals and it will thus work for any kind ofcircuitry and not only on the transistor-level example shown above.

Amplitude Difference Detector

FIG. 5 shows an example amplitude difference detector that is part ofthe amplitude equalization loop of FIG. 4. Its function is to produce anoutput that represents the average power or amplitude difference betweenthe I and Q input signals. This output is used by the control block tosteer the variable gain block(s) in order to equalize the I and Qamplitudes. In order to achieve high image rejection the amplitudeequalization loop must be very accurate. This means that the detectormust be able to measure very small amplitude differences between I and Qaccurately without offset.

If the I and Q signals exist in digital form, the implementation isstraightforward, using for example peak or RMS detection on I and Qfollowed by some averaging. This can be done using commonly knowndigital techniques.

In an analog or mixed implementation, the amplitude difference detectionis subject to mismatches and offsets, which degrade its accuracy.Therefore, instead of using two amplitude detectors, with the mismatchand offset errors that that would entail, only one amplitude detector isused on a time-sharing basis between the I and Q channels. By timemultiplexing the detector, the mismatch error caused by using twodetectors is minimized.

The first blocks in the analogue-input power difference detector are thetwo optional filters as shown in the block diagram in FIG. 5 withassociated timing diagram shown in FIG. 9. Here non-overlap of certainclock-phases is important as detailed in the lower part of the figure.The filters have high pass and low pass characteristics. This filteringis in addition to any channel filtering that might precede the Iin andQin signals. The high pass function ensures that possible DC offset of Iand Q is removed so that it does not interfere with the amplitudedifference measurement. The low pass function provides additionalrejection of jammers if the previous channel filtering has not providedenough rejection already. Because the frequencies of the jammers areoutside the channel filter pass band, the channel filter might itselfcreate additional gain and phase imbalances of the I and Q components ofthe jammers and it might be important to ensure that the amplitudeequalization loop equalizes the amplitude of the desired signal and notthe jammers. This can be achieved by the low pass function of theoptional filters. The low pass corner frequencies are selectable bycontrol signals {bw0} and {bw1} to give adjustable insertion loss andrejection to the adjacent channel, such as sound carriers of analogtelevision signals. If used, these filters must be well matched so thatthe following circuitry is measuring the mismatch in the actual I and Qsignal paths and not the mismatch in the filters. The filters areoptional and may not be necessary in many systems.

The filtered signals are then applied to the following optionalamplifier, alternatively by the {Isel} and {Qsel} signals that turn onand off the switches. The amplifier input (or detector input if theamplifier is not used) is auto-zeroed by the control signal {az} beforeswitching from one channel to another. This is done to prevent crosscoupling between the I and Q filters through the signal storage on theinput capacitance of the amplifier. The auto-zeroing is optional butpreferred.

Next, the switched I/Q signal is passed to an amplitude detector, whichcan be implemented in several known ways, for example as a rectifier,peak detector, squarer, or other known techniques. A current rectifieressentially consists of two rectifying class-AB mirrors, which sourcesor sinks current from the input and mirror it to the output. To improvethe response time (which is needed because the input are currentpulses), a very small quiescent current (50 nA) are biased into theinput MOS transistors. To allow for flexibility, this bias can be turnedoff by asserting the control signal {classB}.

Now the output from the rectifier is proportional to the instantaneousabsolute value of the input I or Q signals depending on which channel isconnected to the optional amplifier. The switch matrix and thesubsequent low pass filter performs the subtraction functions tocalculate the magnitude of I minus the magnitude of Q (|I|−|Q|). To dothis, the input current that represents |I| or |Q| are pumped straightor crossed into the filter, thereby performing the subtraction. Thereare times when the output from the rectifier does not represent the I orQ signal or has not settled yet because of device capacitances. Toreduce the detection error due to these, the input current canoptionally be diverted to rails during these periods and it occurs whenthe control signal {open-} is asserted. During other times, the switchis controlled by the {chop} signal. There is also a switch across theoutput, which is controlled by the control signal {lpfrst}. This can beused to zero the output, which can for example be useful for calibratingoffsets.

The current from the switch matrix not only consist of the desired DCcomponent, which is proportional to the power difference, but also otherfrequency components as well. These frequency components can causealiasing and overload the sigma-delta converter. Thus, it has to beattenuated and it is done by the output low pass filter. The lower thecorner frequency of this low pass filter the better.

In the implementation of FIG. 5, a current-mode implementation is used,in which the output of the rectifier is a current. However, avoltage-mode implementation could equally well be used, in which the lowpass filter is a series RC connection. The low pass filter does notnecessarily have to be a passive RC filter. Any type of filter, activeor passive, can be used. The chopped signal could also be digitized andthe filtering done in the digital domain.

To further reduce static offset at the output, an offset calibrationscheme can be used. During the offset calibration mode, the inputs ofthe operational transconductance amplifier (OTA) is disconnected fromthe I and Q output and shorted to the reference voltage by the optionalcontrol signal {oscal}.

FIG. 10 shows the amplitude and phase calibration used with an upconverter modulator. Alternatively, amplitude and phase calibration canbe placed at the output side of the mixers. This way the errorsintroduced by the mixers and LO signals are also corrected. Thesummation block shown in the drawing can be implemented using the methodfrom FIG. 8.

In a receiver it is preferable to have the I and Q calibration on thebaseband or IF side of the mixers, RF being the input to the mixers.This way the errors introduced by the mixers will be compensated. In atransmitter the calibration is preferably on the RF output side, againto compensate mixer and LO errors.

Control Block

As FIG. 4 shows, the amplitude difference detector provides the input tothe control block, which can be analog, digital, or mixed. In an analogimplementation, a simple integrator can be used (continuous-time ordiscrete time, for example switched-capacitor). It is important thatthis integrator have low offset. This can be achieved either throughgood component matching or by using known offset cancellationtechniques.

In a digital implementation, the control block can be implemented usinga digital integrator.

In a mixed implementation, where the I and Q signal paths are analog butthe control block is implemented digitally, it is advantageous to placethe A/D conversion at the input of the control block. Several types ofknown A/D converter topologies may be used, however it is especiallyadvantageous to use a 1^(st) order ΣΔ converter because of itssimplicity in the analog domain as well as in the digital domain whereit provides a 1 bit wide bit-stream, allowing integrators to beimplemented as simple up-down counters.

1. An amplitude and phase corrector for in-phase (I) andquadrature-phase (Q) signals comprising: first means for amplitudebalancing wherein the I and Q signals are balanced to produce amplitudebalanced I and Q signals; means for summing and differencing theamplitude balanced I and Q signals wherein phase is corrected to producequadrature-phase signals; and second means for amplitude balancingwherein the quadrature-phase signals are balanced to produce amplitudeand phase corrected I and Q signals.
 2. The amplitude and phasecorrector of claim 1 wherein the means for amplitude balancingcomprises: two signal paths, at least one path comprising a variablegain element with a signal input and signal output and having a gaincontrol input; an amplitude difference detector coupled to the signalpaths; control circuitry responsive to the amplitude difference detectorfor driving the gain control input to adjust the variable gain elementto produce equal amplitude in the two signal paths.
 3. The amplitude andphase corrector of claim 2 wherein the amplitude difference detectorcomprises: a switch to alternately select one of the signals; a peakdetector coupled to the switch to detect the amplitude of the selectedsignal; a switch matrix and output filter for computing the amplitudedifference between the alternately selected signals.
 4. The amplitudedifference detector of claim 3 further comprising two input filters forfiltering the two signals before the signals are alternately selected bythe switch.
 5. The amplitude difference detector of claim 4 wherein theinput filters have adjustable corner frequencies to improve rejection ofsignals adjacent to the signals being compared.
 6. A method of amplitudeand phase correction for in-phase (I) and quadrature-phase (Q) signalscomprising the steps of: balancing the amplitude of the I and Q signalsto produce amplitude balanced I and Q signals; summing and differencingthe amplitude balanced I and Q signals to produce phase correctedquadrature-phase signals; balancing the amplitude of the phase correctedquadrature-phase signals to produce amplitude and phase corrected I andQ signals.
 7. An in-phase (I) and quadrature-phase (Q) signal calibratorfor use in a receiver to correct phase and amplitude errors between theI and Q signals output from a quadrature down converter, the signalcalibrator comprising: a first amplitude balancer wherein the I and Qsignals are balanced to produce amplitude balanced I and Q signals; asummer and a differencer applied to the amplitude balanced I and Qsignals wherein phase is corrected to produce quadrature-phase signals;and a second amplitude balancer wherein the quadrature-phase signals arebalanced to produce amplitude and phase corrected I and Q signals. 8.The signal calibrator of claim 7 wherein the amplitude balancerscomprise: two gain elements each with a signal input and signal output,at least one gain element being variable and having a gain controlinput; an amplitude difference detector coupled to the two gain elementsignal outputs; control circuitry responsive the amplitude differencedetector for driving the gain control input to adjust the variable gainto cause the amplitude of the signal output from two gain elements to beequal.
 9. The amplitude and phase corrector of claim 8 wherein theamplitude difference detector comprises: a switch to alternately selectone of the signals; a peak detector coupled to the switch to detect theamplitude of the selected signal; a switch matrix and output filter forcomputing the amplitude difference between the alternately selectedsignals.
 10. The amplitude difference detector of claim 9 furthercomprising two input filters for filtering the two signals before thesignals are alternately selected by the switch.
 11. The amplitudedifference detector of claim 10 wherein the input filters haveadjustable corner frequencies to improve rejection of signals adjacentto the signals being compared.
 12. An image rejection quadraturemodulator for converting in-phase (I) and quadrature-phase (Q) basebandsignals to a radio frequency (RF) signal comprising: means for I and Qlocal oscillator (LO) generation; first means for amplitude balancingwherein the I and Q signals are balanced to produce amplitude balanced Iand Q signals; means for summing and differencing the amplitude balancedI and Q signals wherein phase is corrected to produce quadrature-phasesignals; and second means for amplitude balancing wherein thequadrature-phase signals are balanced to produce amplitude and phasecorrected I and Q signals; and mixing means to mix the balanced I signalwith the I LO and Q signal with the Q LO; and means for summing themixed I and Q signals; whereby a spectral image of the input basebandsignals is rejected in the RF signal.
 13. A signal processing circuitfor computing a mathematical function on first and second differentialinput signals having a positive and negative line, the circuitcomprising: a first differential circuit with a positive and negativeinput and an output; a second differential circuit and with a positiveand negative input and an output; a summing node connected to the firstand second differential circuit outputs; the input signals connect tothe differential circuits wherein the positive line of the firstdifferential input signal is connected to the first differential circuitpositive input and the negative line of the first differential inputsignal is connected to the second differential circuit negative input;and the positive and negative lines of the second differential inputsignal are connected to the first and second differential circuit inaccordance with the desired mathematical function; whereby the mismatchof the differential circuits is cancelled.
 14. The signal processingcircuit of claim 13 wherein the mathematical function is summation andwherein the positive line of the second differential input signal isconnected to the second differential circuit positive input and thenegative line of the second differential input signal is connected tothe first differential circuit.
 15. The signal processing circuit ofclaim 13 wherein the mathematical function is differencing wherein thepositive line of the second differential input signal is connected tothe first differential circuit negative input and the negative line ofthe second differential input signal is connected to the seconddifferential circuit positive input.
 16. The signal processing circuitof claim 13 wherein the differential circuit comprises bipolartransistor pairs.
 17. The signal processing circuit of claim 13 whereinthe differential circuit comprises field effect transistor pairs.
 18. Amethod of computing a mathematical function on first and seconddifferential input signals each having a positive and negative lineusing a differential summation circuit, the method comprising the stepsof: connecting the positive line of the first differential input signalto the first differential summation circuit input; connecting thenegative line of the first differential input signal to the seconddifferential summation circuit input; connecting the positive andnegative lines of the second differential input signal to the tworemaining summation circuit inputs to achieve the desired mathematicalfunction; whereby the cross connection of the differential input signallines to different summation circuit inputs cancels mismatches and gainerrors in the summation input paths.